3DES (Triple DES) / DES (VHDL)

Project maintainers


Name: 3des_vhdl
Created: Oct 27, 2006
Updated: Dec 20, 2009
SVN Updated: Mar 10, 2009
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 0 reported / 0 solved
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Other project properties

Category:Crypto core
Development status:Stable
Additional info:FPGA proven
WishBone compliant: No
WishBone version: n/a


This is a VHDL implementation of Triple-DES (pipelined) and DES cryptographic algorithms, as recommended by NIST.

In our tests the core has been verified to comply with the (NIST FIPS 46-3) (DES)recommendation.

This core is provided by: (Coretex Systems, LLC)


- Pipelined architecture.

- VHDL source code.

- Verified in hardware.

- Small footprint (the numbers are for Xilinx Virtex 2 FPGA)
- 1742 slices,
- 302 IOBs,
- no block RAMs,
- 1 GCLK.

- Fast processing (the numbers assume the pipeline is fully utilized)
- An output each 17 clocks.
- Maximum operating frequency 162 MHz.
- Bandwidth ~581 Mb/s.


- The code is verified, documentation to be added.
- We are working on an extension to support the Wishbone interface.