A MC68HC08 clone in VHDL as single file. Twice performance as the original. Multiplication is done in one clock cycle. Division in two clock cycles.
- feature1
- feature1.1
-feature1.2
-feature2
tested with C compiler works OK with interrupts
2009.07.16 new version, bugfix at opcode 7E mov ,X+,opr8a X post increment fixed