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ARINC 429 Transmitter and Receiver :: Overview

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Details

Name: a429_transmitter_receiver
Created: Aug 15, 2019
Updated: Aug 16, 2019
SVN Updated: Aug 16, 2019
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 0 reported / 0 solved
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Other project properties

Category:Communication controller
Language:Verilog
Development status:Beta
Additional info:Design done, FPGA proven
WishBone compliant: No
WishBone version: n/a
License: Others

Description

ARINC 429 is the most widely used avionics communication standard for commercial aviation.

The aim of this project is to provide a set of ARINC-429-compatible TX and RX synthesizable interfaces. The transmitting interface serializes a 32-bit A429 word with the appropriate timing and encoding characteristics whereas the receiving interface samples serialized data, providing the decoded 32-bit words at the output. This implementation does not include any particular CPU bus interface (i.e. Wishbone, etc.), leaving the option for any designer to make it as complex or simple as required for their application.

As happens with other serial communication protocols, ARINC 429 needs for external line driver and receiver circuits to obtain the electric signaling levels required by the standard.

Features

  • Single 2MHz master clock operation.
  • Generic parallel interface.
  • Selectable bit rate (12.5Kb/s or 100Kb/s).
  • Optional parity bit check (RX).
  • ARINC 429 word formatting (incl. 'label' field bit reversal).

Status

Synthesizable, FPGA-tested Verilog code available under the MIT License. Parity bit generation option (TX interface) is not implemented yet.