AES encryption all keylength
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Details
Name: aes_all_keylength
Created: Jun 24, 2013
Updated: Feb 5, 2017
SVN Updated: Sep 15, 2014
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 0 reported / 0 solved
Created: Jun 24, 2013
Updated: Feb 5, 2017
SVN Updated: Sep 15, 2014
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 0 reported / 0 solved
Star2you like it: star it!
Other project properties
Category:Crypto core
Language:VHDL
Development status:Alpha
Additional info:
WishBone compliant: No
WishBone version: n/a
License: BSD
Language:VHDL
Development status:Alpha
Additional info:
WishBone compliant: No
WishBone version: n/a
License: BSD
Description
Four stage pipeline design working at 361.890MHz on Xilinx's 28nm Kintex 7 speed grade 3 FPGA device. Calculating 4 blocks parallely, encrypting up to 4.25 Gbits data per second (0.361Ghz* 4 stage pipe * 128 bits parallel / 44 cycles a block).
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