TI TLV320AIC1106 PCM Codec Altera Avalon IP core
Project maintainers
Details
Created: Feb 18, 2019
Updated: Feb 27, 2019
SVN Updated: Feb 28, 2019
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 0 reported / 0 solved
Other project properties
Language:Verilog
Development status:Stable
Additional info:Design done, FPGA proven
WishBone compliant: No
WishBone version: n/a
License: LGPL
Description
AIC1106-IPcore
This is Altera Avalon IP core for TI TLV320AIC1106 PCM Codec With Microphone Amps & Speaker Driver.
Git hub project home: https://github.com/alexo-git/AIC1106-IPcore
Hardware:
The AIC1106 IP core receive/transmit audio data from/to CPU with standard Avalon staream sink/source. Also the IP core have mode/status register implemented as Avalon memory mapped register.
Format of the mode/status register:
Read:
| 31..6 | 5 | 4 | 3 | 2 | 1..0 |
|---|---|---|---|---|---|
| 0 | underflow_r | mute | reset_n | 0 | volume |
Write:
| 31..6 | 5 | 4 | 3 | 2 | 1..0 |
|---|---|---|---|---|---|
| 0 | reset | loopback | enable | mute | volume |
Normally, the stream sink/source interface should be connected to separate FIFO buffers implemented as on-chip FIFO memory. The FIFO buffer, in turn, is connected to the system bus of the processor.
Software:
When FIFO buffers near to full/empty it fire interrupt and software driver is responsible for read/write FIFO buffers to keep audio staream continuouse.
During driver initialization, it registered as new device /mnt/audio/ and being accessible as regular file.
Driver also capable to read/write standard .wav file.
For details, please explore files audio_drv.c and audio_drv.h