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Name: alt_isa
Created: Mar 2, 2020
Updated: Dec 11, 2020
SVN Updated: Mar 7, 2020
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 0 reported / 0 solved
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Other project properties

Category:Processor
Language:VHDL
Development status:Planning
Additional info:Specification done
WishBone compliant: No
WishBone version: n/a
License: LGPL

Description

Alt_ISA is an OpenCores processor project collecting a variety of “alternative” Instruction Set Architectures. These are variations on existing ISAs. The variations are intended to improve some aspects thought to be limiting or incomplete. This project is large: eight distinct ISAs each with a full complement of op-codes. Current status is somewhere between planning and fully defined or specified. In each case there is a justification document which may or may not contain a full description. There are spreadsheets showing the instruction formats and the associated op-codes.

NEW: Most recent work at https://github.com/jimbrake/ROC32_8. Two of the ISAs (ROC32_8, was alt_risc & STKOC32_8) use two bits of the op-code to indicate instruction length, remaining six bits are the primary op-code.

Five bit register fields can be used (via instruction option/bit) to specify a variable length immediate value (that follows the instruction).

Formal nomenclature: RISC becomes Register Oriented Computer Architecture, CISC becomes Memory Oriented Computer Architecture, Hybrid register/memory architecture becomes Register And Memory Oriented Computer Architecture, Stack machine becomes Stack Oriented Computer Architecture, etc.

A specific architecture instance has a register file word/address size and an addressable memory unit size. Instruction size(s) and register file size not encoded. Examples: ROC32_8 RISC, 32-bit registers and 8-bit byte addressing. RMOC48_12 CISC, 48-bit registers and 12-bit "byte" addressing, register/memory hybrid STKOC36_9 36-bit registers and 9-bit "byte" addressing, stack/accumulator hybrid

The url of the svn repository is: https://opencores.org/websvn/listing/alt_isa/alt_isa

Alt_ISA Introduction The list of alt-ISAs is: alt_msp430, alt_risc, alt_vax, alt_x86, alt_stk-accum and altA (was quad_ISA). All except alt_msp430 support four data sizes.

alt_msp430: The Texas Instruments MSP430 ISA is limited to 8 and 16-bit data. Here the ISA is pruned to provide op-code space to support three data sizes. The register file word size is increased to that of the largest data size, say 24 or 32 bits, providing convenient access to 16MB or 4GB of addressable memory. The MSP430 memory addressing modes are register, register indirect, register indirect post increment and register offset modes. The missing register indirect pre-decrement mode is provided by limiting the number of registers to fourteen: 5 14 14 = 980 which fits into ten bits. The remaining codes are used for relative, immediate, absolute and “frame” address modes. Six bits of op-code and three data sizes limits what can be squeeze into a 16-bit instruction. The expanded instruction is 24-bits with variable length immediate values following either the 16 or 24 bit instructions.

ROCm_n: Typical RISC ISAs use a 32-bit instruction size. Alt_RISC offers a 24-bit instruction size thereby improving code density to that found in good code density ISAs. As currently planned instructions have four sizes, 24, 32, 40 or 48 bits. The 24-bit instructions have a 6-bit op-code, three register fields and a bit indicating the second operand is immediate. The five bit immediate field encodes either a four bit unsigned value, an eleven bit signed value or a one to eight byte value (additional immediate bytes follow the instruction). The 32-bit computation instructions include and additional eight bits for operand invert/complement control, one bit for status register update and five bits for conditional execution (predication). The 32-bit load/store instructions include base, index and offset register fields along with index register scaling. m is register and ALU size, n is "byte" size.

STKOCm_n: An attempt to overcome some of the limitations of stack and accumulator architecture in the age of out-of-order pipelined computer architecture. Code density is maximized by allowing a single register field along with an op-code. The key to OOO performance is to make the stack items write once with stack space reclamation at subroutine exit (with two register operands one has a "belt" machine). The 16-bit instruction has a two bit length field (of 00), a six bit op-code, a five bit register reference and three bits for: immediate operand, replace operation to register file and push/pop of the accumulator/stack top. Longer instructions allow for predication, larger register field and instruction set expansion. m is register and ALU size, n is "byte" size.

alt_vax: The DEC VAX has been criticized for generating as many as 15 memory faults in a single instruction. Alt_vax limits a single instruction to one memory location reference. The instruction format can then be simplified to a single 24-bit instruction: three 4-bit register fields, an 8-bit op-code and the remaining four bits used to specify one of five address modes (see alt_msp430) and which register field is so used (three choices).

alt_x86: An encoding of x86-64 instructions with both RISC and x86 functionality.

altA: An architecture supporting several ISA types:

Stack instructions use the register file to hold a portion of a data and a return stacks and an area for frame variables. Part of the instruction has the op-code and the other part the offset from the data/return/frame pointer. Instructions are 16-bits.

RISC instructions have three five bit register fields and take 24-bits.

X86 instructions have three five bit register fields: the register file data item, the register file memory pointer and the index register to be applied to the memory pointer. Instructions are either 24 or 32-bits, 32-bits needed when using scaled index addressing. For a full X86 super set both RISC and X86 instruction formats are used.

Up to 64 macro instructions can be defined using a lookup table. A table entry can consist of more than one instruction. User register fields are supported.

The several kinds of altA instructions can be encoded in any sequence.