AltOr32 - Alternative Lightweight OpenRisc CPU

I had trouble running the main makefile in the project on OSX. The problem was traced to rtl>sim_icarus>makefile, with the line:

compile :
    $(VERILOG_CMD) -o output.out $(SRC) $(INC_DIRS) $(SRC_FLAGS) 

The fix is simply to move $(SRC) to the end of the line:

compile :
    $(VERILOG_CMD) -o output.out $(INC_DIRS) $(SRC_FLAGS) $(SRC)