Created: Jun 9, 2012
Updated: Feb 15, 2015
SVN Updated: Jun 29, 2014
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Other project properties
AltOR32 is an OpenRISC 1000 architecture derived RISC CPU targeted at small FPGAs and contains only the most basic ISA features from the OpenRisc project.
Instructions & registers relating to Vector, floating-point, 64-bit extensions, MMU & Cache have been omitted.
The aim of AltOR32 is to provide a simple 32-bit soft CPU architecture aimed at control applications that can fit in low-end FPGA technology.
This design implements all instructions that cannot be disabled. Anything else is viewed as beyond the scope of this cut-down soft-CPU implementation.
AltOR32 does not make use of delay slots, unlike the original OpenRisc implementation.
Due to this, the or1knd toolchain is required.
The project contains a Verilator cycle accurate model of the CPU which can execute the same code as the simulator. Waveforms can be outputted and viewed in GTKWave.
- Pipelined Verilog core with optional instruction & data cache.
- Synthesizes to ~100MHz on a Xilinx Spartan 6 LX9 -3
- Harvard architecture (separate instruction & data cache / memory interfaces).
- Support for interrupts & tick timer.
- Also non-pipelined 'lite' version available.
Instruction Set Simulator
- A simple simulator for OpenRisc instructions.
- Able to execute OpenRisc 1000 (ORBIS32) code compiled with the following options:
-msoft-div -msoft-float -msoft-mul -mno-ror -mno-cmov -mno-sext
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