Basic RSA Encryption Engine

Description

This core is strictly an encryption/decription engine. No attempt has been made to incorporate key generation, and no plans exist to do so.

The core accepts a 1024-bit exponent, a 1024-bit modulus, and a 1024-bit message. After about 1 million clock cycles, it returns the encrypted or decrypted message on the output bus. There is nothing pretty, fast, or efficient about its operation. It simply uses a brute force approach to perform the required modular exponentiation. Operation is described in more detail in comments in the source.

BasicRSA was written in VHDL using Xilinx's ISE 5.2i. It has been tested using ModelSim XE for 32-bit data, but has not been verified for larger bus widths, nor has it been tested in actual hardware. This core is intended primarily as a learning vehicle for me, and any comments or suggestions to make it better will be appreciated.

Features

- It works for up to 1024-bit modulus (Tested at 32-bit modulus).
- It fits in a Xilinx Virtex II XC2V8000.
- Clock Rate at 32-bit modulus approximately 16MHz.
- Clock Rate at 1024-bit modulus approximately 10MHz.
- Cycles required to complete operation at n-bit modulus, slightly greater than n-squared clocks.

Status

- Long carry chains in adders and subtracters are the main reason for the low clock rates.
- Experimentation has determined that carry lookahead adders automatically synthesized by ISE are about as good as it gets. Pipelining partial adders could improve throughput, but only at a tremendous cost in gate count.
- Project status has been changed to "Stable" because no improvements have been discovered or suggested to the author.