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Details

Name: baudgen
Created: Dec 5, 2007
Updated: Dec 20, 2009
SVN Updated: Mar 10, 2009
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 0 reported / 0 solved
Star2you like it: star it!

Other project properties

Category:Communication controller
Language:VHDL
Development status:Stable
Additional info:FPGA proven
WishBone compliant: No
WishBone version: n/a
License: GPL

Description

Ever needed a pulse at a given frequency ( period ).

Well that is what BaudGen gives you.

By the use of parameters, you specify the frequency of the clock you wish to divide, the period ( baud rate ) you wish out, and optionally, how fast you want an over sample output.

BaudGen works out the required count values, and outputs one clock wide pulses at the required rate.