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Name: darkriscv
Created: Jan 27, 2021
Updated: Feb 14, 2021
SVN Updated: Feb 14, 2021
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 0 reported / 0 solved
Star1you like it: star it!

Other project properties

Category:Processor
Language:Verilog
Development status:Stable
Additional info:Design done, FPGA proven
WishBone compliant: No
WishBone version: n/a
License: BSD

DarkRISCV

Developed in a magic night of 19 Aug, 2018 between 2am and 8am, the DarkRISCV softcore started as an proof of concept for the opensource RISC-V instruction set. After years of development and lots of contributions from friends, the current state is a 3-stage pipeline running up to 400MHz in a overclocked Kintex Ultrascale (or 100MHz for a cheap Spartan-6) and lots of features:

  • implements most of the RISC-V RV32I instruction set (missing csrx, ex and fencex)
  • works up to 400MHz (overclocked kintex ultrascale, up to 100MHz in a cheap spartan-6)
  • sustain 1 clock per instruction most of time
  • flexible harvard architecture (easy to integrate a cache controller)
  • works fine in a real xilinx and lattice FPGAs
  • works fine with gcc 9.0.0 for RISC-V (no patches required!)
  • uses between 1000-1500LUTs, depending of enabled features (Xilinx LUT6)
  • optional RV32E support (works better with LUT4 FPGAs)
  • optional 16x16-bit MAC instruction (for signal processing)
  • optional coarse-grained multi-threading (MT)
  • no interlock between pipeline stages
  • BSD license: can be used anywhere with no restrictions!

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