Soon Chong, Lai

DDR3 Synthesizable BFM

## Description

This is a fully synthesizable DDR3 Memory BFM. Implemented using Verilog 2001 without any vendor specific IP Block. As such, the BFM is not able to run a very high speed. Test shown that is is able to respond to WRITE and READ instruction at 10MHz.

## Status

Memory BFM has been tested and passes all Micron DDR3 testbench. It is also has been tested and able to passes Altera DDR3 Testbench.Has been synthesized using Xilinx ISE 13.2 and Quartus II Version 11.1 Build 173


<h2 id="description">Description</h2>
<p>This is a fully synthesizable DDR3 Memory BFM. Implemented using Verilog 2001 without any vendor specific IP Block. As such, the BFM is not able to run a very high speed. Test shown that is is able to respond to WRITE and READ instruction at 10MHz. </p>
<h2 id="status">Status</h2>
<p>Memory BFM has been tested and passes all Micron DDR3 testbench. It is also has been tested and able to passes Altera DDR3 Testbench.Has been synthesized using Xilinx ISE 13.2 and Quartus II Version 11.1 Build 173</p>


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DDR3 Synthesizable BFM

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