Generic FIR Filter
Project maintainers
Details
Name: fir_wishbone
Created: Sep 10, 2013
Updated: Dec 1, 2015
SVN Updated: May 3, 2018
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 0 reported / 0 solved
Created: Sep 10, 2013
Updated: Dec 1, 2015
SVN Updated: May 3, 2018
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 0 reported / 0 solved
Star5you like it: star it!
Other project properties
Category:DSP core
Language:VHDL
Development status:Beta
Additional info:FPGA proven
WishBone compliant: No
WishBone version: n/a
License: LGPL
Language:VHDL
Development status:Beta
Additional info:FPGA proven
WishBone compliant: No
WishBone version: n/a
License: LGPL
Description
This FIR filter is very generic and flexible. It has been tested working on an FPGA, though the existing version does not yet have a Wishbone control interface. I will be adding one to it soon. Stay tuned!
The impulse response curves for both theoretical calculations (Sage Math and ModelSim / Questa) vs. hardware acquisition results correlate well against each other.
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