Fuzzy Logic Hardware Accelerator

Description

This project is to design a Fuzzy Logic Hardware Accelerator (FLHA) that is WishBone compatible. FLHA is capable of generating fuzzy rule matrix and inference for it. The input and output data will be 64-bit. Each input and output data will have 8 elements in each universal space, and each degree of membership is a discreet set of 256 members from 0 to 1. For the rule matrix, it can either generate it based on the input data or directly input it to its matrix. When the rule memory has already builded, a master can read the whole matrix from this FLHA. For inference, the output will be based on the input and the rule matrix. This FLHA should be smart enough to tell the master (requester) about its status: done, rule building busy, inference busy, error, etc.

Features

- Capable of building and storing fuzzy rules using standard composition rule.
- Using interpolation method to obtain the inference result.
- Input and output data will have 8 elements in each universal space, and each degree of membership is a discreet set of 256 members from 0 to 1. Current plan is that fuzzification and defuzzification of data are done by the host (master). I might add defuzzification to the model in the future.
- Device has to be smart enough to indicate its status, such as done, rule building busy, inference busy, etc, when requested by the host (master).
- WishBone compliant.

Status

- FLHA's core is done. Simulated on ModelSim XE II 5.7c. Looks fine. Help me to improve, or find any bugs. Thanks.
- Start to work on the WishBone interconnect.