c - VHDL Co-Simulation with FLI

Description

Using ModelSim Foreign Language Interface for c - VHDL Co-Simulation and for Simulator Control on Linux x86 Platform

Writing testbenches in VHDL can be very cumbersome. This can be solved by using a programming language with more features that does not need to bother about hardware implementation restrictions. This project demonstrates how plain c can be used for testing. Besides generating Stimuli and Analyze results, optional features, like a control interface and simulation accelerators, have been added to this testbench environment.

code can be found on
https://github.com/andrepoolfli