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Details

Name: forwardcom
Created: Nov 3, 2021
Updated: Nov 5, 2021
SVN Updated: Nov 6, 2021
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 0 reported / 0 solved
Star1you like it: star it!

Other project properties

Category:Processor
Language:Verilog
Development status:Alpha
Additional info:FPGA proven, Specification done
WishBone compliant: No
WishBone version: n/a
License: CERN-OHL-L

ForwardCom

A forward compatible CPU with variable-length vector registers

Introduction

ForwardCom is a project for development of a new open instruction set architecture and the corresponding open hardware and software standards for high performance microprocessors and vector processors. The intention is to make experiments and to investigate what an ideal computer architecture may look like and to develop a complete open computer system that is more efficient than the currently prevailing systems, such as x86, ARM, etc. ForwardCom is also useful as a high-end alternative to RISC-V and OpenRISC. Starting from scratch and making a complete vertical redesign allows us to learn from the history of past mistakes and get rid of the heritage of old quirks that hamper contemporary systems.

Highlights

  • The ForwardCom instruction set is neither RISC nor CISC, but a new paradigm with the advantages of both. ForwardCom has few instructions, but many variants of each instruction. This makes the code more compact and efficient with more work done per instruction
  • The ForwardCom design is scalable to support small embedded systems and system-on-a-chip designs, as well as large supercomputers and vector processors without losing binary compatibility
  • The instruction set is fully orthogonal. The same instruction can be coded with integer operands of different sizes and floating point operands of different precisions. The operands can be scalars or vectors of any length. Operands can be registers, memory operands with different addressing modes, or immediate constants
  • Vector registers of variable length are provided for efficient handling of large data sets
  • Array loops are implemented in a new flexible way that automatically uses the maximum vector length supported by the microprocessor in all but the last iteration of a loop. The last iteration automatically uses a vector length that fits the remaining number of elements. No extra code is needed to deal with remaining data and special cases. There is no need to compile the code separately for different microprocessors with different vector lengths
  • No recompilation or update of software is needed when a new microprocessor with a different vector register length becomes available. The software is guaranteed to be forward compatible and take advantage of the longer vectors of new microprocessor models without recompilation
  • Strong security features are a fundamental part of the hardware and software design
  • Memory management is simpler and more efficient than in traditional systems. Various techniques are used for avoiding memory fragmentation. There is no need for memory paging and translation lookaside buffer (TLB). Instead, it is possible to use a memory map with a limited number of sections with variable size. All code is position-independent
  • There are no dynamic link libraries (DLLs) or shared objects. Instead, there is only one type of function libraries that can be used for both static and dynamic linking. Only the part of the library that is actually used is loaded and linked. The library code is kept contiguous with the main program code in almost all cases. An executable file can be re-linked to update a function library or to adapt the program to a particular hardware configuration, operating system, or user interface framework
  • A mechanism for calculating the required stack size is provided. This can prevent stack overflow in most cases without making the stack bigger than necessary
  • A mechanism for optimal register allocation across program modules and function libraries is provided. This makes it possible to keep most variables in registers without spilling to memory. Vector registers can be saved in an efficient way that stores only the part of the register that is actually used
  • Standards for software tools, ABI, file formats, system libraries, etc. are defined in order to establish compatibility between different programming languages and different platforms. It is possible to code different parts of a program in different programming languages
  • Development tools and softcore available with open licenses

The svn repository of ForwardCom is at: https://opencores.org/websvn/listing/forwardcom/forwardcom

The website https://www.forwardcom.info describes the ForwardCom instruction set and the goal of the ForwardCom project.

A complete manual of the ForwardCom project is at https://opencores.org/ocsvn/forwardcom/forwardcom/manual/forwardcom.pdf

A git mirror is at https://github.com/ForwardCom