Floating-point FFT/IFFT

Description

This project is the special floating-point Fast Fourier transform realization. Floating point representation has only 24 bits and takes into account the features of the Xilinx FPGA devices. FP24 is the reduced format of IEE 754. The word in FP24 format has 16-bit fraction, 1-bit sign and 7-bit exponent. It gives the best resource usage of the FPGA such as DSP48E1 and RAMB18E1. There is a word format:

A = 2^(EXP(A)) * (-1)^SIGN(A) * FRAC(A), where

EXP(A) - 7-bit exponent (0-127),
SING(A) - 1-bit sign (0 - positive, 1 - negative),
FRAC(A) - 16-bit fraction (0-13071).

Some special arithmetic was developed for FP24 format: fix2float, addition, subtraction, multiplication, float2fix. The feature of FP24 arithmetic is the absence of the shift registers for a result calculation.

The FFT core is fully pipelined and has radix-2 format representation. FFT project used the DIF (decimation in frequency) method, and IFFT used DIT (decimation in time) method. This is the simplest and most common form of the Cooley–Tukey algorithm. FP24FFTK core implemented by using the most common used algorithm from "Theory and Application of Digital Signal Processing" by Lawrence R. Rabiner and Bernard Gold.

The FFT/IFFT core consists of the butterfly, delay lines and a twiddle factor ROM storage. So the butterfly for FFT implemented by DIF algorithm, and for IFFT by DIT algorithm.
Delay lines has 3 stages: a short, a medium and a long. Short stages use SRL16 and SRL32 shift registers. Medium stages use chain of SRL32 shift registers. Long stages use RAM18E1 with different address/data width.
Twiddle factor storage also has some stages for keeping data in ROM. The lowest stages use distributed logic and the medium stages use RAMB18E1 blocks. So the highest stages use Taylor approximation for economy of RAMB18E1 resources (not done yet).

The big advantage of the chain FFT-IFFT project is it does not require bit-reverse buffer. For example if the input data on FFT has natural order format, so the data on the output of IFFT also has natural order format. You don't need to use bit-reverse transform after FFT calculation (but data has bit-reverse format). This advantage can save many RAMB block in your FPGA device.

Main Features:
- Pipelined floating point FP24 format representation;
- FP24 arithmetic operations: addition, subtraction, multiplication, fix2fp, fp2fix;
- 1K-64K-point radix-2 FFT;
- Forward and inverse FFT: FFT/IFFT;
- Bit-reverse for chain FFT-IFFT doesn't required.
- Economy RAMB18E1/DSP48E1 usage.

The FP24FFTK core works only with the latest Xilinx FPGA devices: Virtex-6 and 7 series (Artix, Kintex, Virtex).
You should change DSP48E1 in source codes if you want to use this project with Virtex-4 or Virtex-5 devices.

FP24FFTK project with N = 65535 points is calculated on Xilinx XC6VSX315-2 FPGA at least 266 MHz clock cycle.
This core can be used in Radar stations (for example for fast convolution), OFDM systems, SDR (software defined radio), etc.

I've tested chain FFT-IFFT plus SF (Support function) to Chirp signals in "Pulse Compression system".

Known problems:

1. Taylor twiddle factor isn't done yet. Some coefficients are repeated k-times.
2. Medium delay lines use Xilinx CoreGenerator files. It need to replace on an own shift register.
3. FFT less than 1K isn't done. I suppose that this is not big problem for this project.


Please, contact me if find any bugs and can help me with solving known problems.