The HiCoVec processor is based on a simple 32 bit scalar unit and connected with a vector unit for SIMD operations.
The amount of data simultaneously processed in the vector unit can be configured as well as the amount of vector registers to hold the data. It is also possible to activate/deactivate some functions (like hardware multiply) of the CPU to gain performance or decrease logic required.
The processor has its own instruction set. One instruction word is divided into a scalar and a vector part. This makes it possible to execute two commands (each in one unit) at the same time. It is also possible to execute commands that require cooperation of scalar and vector unit.
The processor comes with its own on-chip-debugging-unit as well as an assembler. It has been validated and tested in a Xilinx Spartan 3 FPGA.
HiCoVec was originally developed within the scope of Harald Manske's diploma thesis under the guidance of Prof. Dr. Gundolf Kiefer. It is further developed at the Computer Engineering Lab at the University of Applied Sciences in Augsburg.
More information and the latest updates can be found here: http://www.hs-augsburg.de/~kiefer