HiCoVec - a configurable SIMD CPU


Name: hicovec
Created: May 22, 2008
Updated: Feb 25, 2010
SVN Updated: Mar 10, 2009
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 0 reported / 0 solved
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Other project properties

Development status:Beta
Additional info:FPGA proven
WishBone compliant: No
WishBone version: n/a
License: GPL

HiCoVec - a configurable SIMD CPU

The HiCoVec processor is based on a simple 32 bit scalar unit and connected with a vector unit for SIMD operations.

The amount of data simultaneously processed in the vector unit can be configured as well as the amount of vector registers to hold the data. It is also possible to activate/deactivate some functions (like hardware multiply) of the CPU to gain performance or decrease logic required.

The processor has its own instruction set. One instruction word is divided into a scalar and a vector part. This makes it possible to execute two commands (each in one unit) at the same time. It is also possible to execute commands that require cooperation of scalar and vector unit.

The processor comes with its own on-chip-debugging-unit as well as an assembler. It has been validated and tested in a Xilinx Spartan 3 FPGA.

HiCoVec was originally developed within the scope of Harald Manske's diploma thesis under the guidance of Prof. Dr. Gundolf Kiefer. It is further developed at the Computer Engineering Lab at the University of Applied Sciences in Augsburg.

More information and the latest updates can be found here:


- standalone 32 bit scalar cpu

- configurable vector extension

- memory interface for SRAM

- on-chip debugging unit

- assembler availiable


HiCoVec is validated and ready to use!

There still is documentation that has to be translated into english. However, the most important documents are done.


- LD - load
- ST - store
- ADD - add
- ADC - add with carry
- INC - increment
- SUB - subtract
- SBC - subtract with carry
- DEC - decrement
- AND - logic and
- OR - logic or
- XOR - logic xor
- LSL - shift left, insert 0
- LSR - shift right, insert 0
- ROL - shift left, insert carry
- ROR - shift right, insert carry
- MUL - multiply (optional command)
- JMP - jump
- JAL - jump and link (for subprograms)
- JZ - jump if zero
- JNZ - jump if not zero
- JC - jump if carry
- JNC - jump if not carry
- CLZ - clear zero
- SEZ - set zero
- CLC - clear carry
- SEC - set carry
- HALT - stop execution of commands
- NOP - no operation

- VNOP - no vector operation
- MOV - copy data from vector to scalar unit
- MOV - copy data from scalar to vector unit
- MOVA - copy data k times into vector unit
- VLD - vector load
- VST - vector store
- VMOV - copy vector registers
- VMOL - shift datawords in vector register one word left
- VMOR - shift datawords in vector register one word right
- VADD - vector add
- VSUB - vector sub
- VAND - vector logic and
- VOR - vector logic or
- VXOR - vector logic xor
- VLSL - vector shift left, insert 0
- VLSR - vector shirt right, insert 0
- VMUL - vector multiply
- VSHUF - shuffle data of two vector registers