High Speed SDRAM Controller With Adaptive Bank Management and Command Pipeline

Description

HSSDRC IP core is the configurable universal SDRAM controller with adaptive bank control and adaptive command pipeline.

HSSDRC IP core and IP core testbench has been written on SystemVerilog and has been tested in Modelsim.

HSSDRC IP core is licensed under MIT License

Features

The main features of HSSDRC IP core are :

- Adaptive SDRAM bank control: command sequence is depending upon previous accesses to the RAM.

- Adaptive command pipeline control: bank control commands for following memory access commands are pipelined into previous command processing chain whenever possible.

- Controller structure is adapted to SDRAM parameters referenced by static timings as parameters

- Configurable time interval for bus turnaround (BTA)

- Overlapping command and data processing

- Variable transaction burst from 1 to 16

- Full SDRAM bandwidth usage for linear sequential access without bus turnaround, bank or row change

- Interfaces configurable via parameters

- Registered input and output control signals except command response line

- Registered data control signals

- Internal timer for auto-refresh process

- Two configurable auto-refresh windows

- Internal logic for transaction ordering ID tags

- Flexible choose of trade-offs between bandwidth/frequency/resources

Status

- Tested in software simulation with Modelsim

- Some synthesis results:
- Quartus 7.2sp1 Cyclone II 710LC @ 144MHz (full performance)
- Quartus 7.2sp1 Cyclone II 630LC @ 185MHz (least performance)

TODO

- Test in hardware with Altera Cyclone II/III and Xilinx Spartan3e FPGA

- Create common ram wrappers for use HSSDRC IP Core

- Create wishbone interface unit for use HSSDRC IP Core

- Create AMBA AXI interface unit for use HSSDRC IP Core

- Create DDR/DDR2 memory controllers IP Core based upon HSSDRC IP Core