I2S to Paralell ADC/DAC controller :: Overview

Project maintainers


Name: i2sparalell
Created: Dec 17, 2005
Updated: Dec 20, 2009
SVN Updated: Mar 10, 2009
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 0 reported / 0 solved
Star1you like it: star it!

Other project properties

Category:Communication controller
Development status:Beta
Additional info:FPGA proven
WishBone compliant: No
WishBone version: n/a
License: GPL

I2S to Paralell ADC/DAC controller

This provides a bridge between a paralell device (such as a microcontroller (uC) and an I2S (!not! I2C) audio bus, generally used for ADC's and DAC's, such as in DVD & MP3 players

Nominal target is a CPLD, 128-cell variants will hold the entire project for bidirectional (ADC & DAC) operation simultaneously with 24-bit I/O's. Removing either side or reducing bus width allows operation in 64-cell devices (the core was actually tested in this configuration).

Origonally written in VHDL for Xilinx ISE - project & constraints file included.


This project may have bugs due to adaptation / cleanup from origonal production core into something of more general interest. Origonal core only used 8 of 24-bits for fitting into 64-cell devices.