riou, sebastien

Iso7816_3_Master

## Description

This project aims at implementing a basic iso7816:3 master which can be controlled by software or by a state machine.  
This is a work in progress. Currently, a draft implementation is being crafted just to identify the design challenges.  
Once it is completed, the plan is to make a precise spec of a final version and then implement it.  
  
Currently the IP supports only T=0, in direct and inverse convention. It does not handle T=0 parity error signaling / retry mechanism yet.  
  
FPGA test included only the UART, not the master module.


<h2 id="description">Description</h2>
<p>This project aims at implementing a basic iso7816:3 master which can be controlled by software or by a state machine.<br />
This is a work in progress. Currently, a draft implementation is being crafted just to identify the design challenges.<br />
Once it is completed, the plan is to make a precise spec of a final version and then implement it.<br />
<br />
Currently the IP supports only T=0, in direct and inverse convention. It does not handle T=0 parity error signaling / retry mechanism yet.<br />
<br />
FPGA test included only the UART, not the master module.</p>


Browse

Iso7816_3_Master

Project maintainers

Details

Other project properties

Description