JPEG Hardware Compressor

I have a final project as same as your JPEG Hardware Compressor. Basically, I'm doing the same, JPEG image compression in actual hardware by using FPGA (NEXYS3) as a hardware, and XILINX as a software. I need a code that can be synthzisable and it can generate a bitstream that can be downloaded into the FPGA.
I saw you caode in the download but they are not 9 vhdl file as you mentioned i
Can you plz help me with this?

help

Hi am using xilinx ise 10.1, unfortunately i cannot find 2-D DCT core in xilinx coregen....can you please tell me which ISE i should use ? nd some steps to simulate ...thank you

JPEG Compression

Good afternoon,

I used the JPEG Hardware Compressor and tested it thanks to the Xilinx ISE Project navigator. It was running well with a Virtex 2 XC2V1000-4 but it used more hardware resources than you announced and it can't be implemented in the XC2V1000-4.
I tried with a XC2V1500-4 and it was OK. 

I don't know why there is those differences of compilation between your work and mine, have you got some ideas about that? What compiler did you use for your test?

I Thank you in advance.

Julien Morel
Polytech'Orléans

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JPEG Hardware Compressor