Watson, Albert

Fazzino, Fabrizio

M1 Core

## M1 Core briefly...

The M1 Core is a 32-bit RISC CPU compatible with a popular GCC target.  
It's been designed for simplicity and it's been used for some didactical activities at the University of catania.  
The CPU is written in Verilog and it's been tested on FPGA (Xilinx Spartan-3E Starter Kit).  
The CVS tree includes sources from other two OpenCores projects:

-   [**wb\_ddr**](http://opencores.org/project,wb_ddr,overview) developed by Joerg Bornschein
-   [**ps2\_interface**](http://opencores.org/project,ps2,overview) developed by John Clayton


<h2 id="m1-core-briefly">M1 Core briefly...</h2>
The M1 Core is a 32-bit RISC CPU compatible with a popular GCC target. 
It's been designed for simplicity and it's been used for some didactical activities at the University of catania. 
The CPU is written in Verilog and it's been tested on FPGA (Xilinx Spartan-3E Starter Kit). 
The CVS tree includes sources from other two OpenCores projects:
<ul>
<li><a href="http://opencores.org/project,wb_ddr,overview">wb_ddr</a> developed by Joerg Bornschein</li>
<li><a href="http://opencores.org/project,ps2,overview">ps2_interface</a> developed by John Clayton</li>
</ul>

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M1 Core

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M1 Core briefly...