vl, tgr

Kranenburg, Tamar

MB-Lite

The project overview says "synthesized for an Altera board as well to show platform independence" but I have tried compiling with Altera Quartus 11.0sp1 (and Intel Quartus Lite 16.1) for a Cyclone IV E FPGA board and while it does build without errors it doesn't pull in the whole design like the Xilinx ISE.

Can you post the .qpf and .qsf used to build on Quartus and/or instructions for Quartus?

Build for Altera

Hi,
I use the mblite with Xilinx XPS 10.1 and the GNU C - compiler. The environment(PLB - bus) is adapted and can be substituted to the original microblaze.  

But it doesn't run correctly.  
asm("    lbui    r3, r6, 0");
asm("    sbi     r3, r4, 0"); // Error

asm("    lbui    r3, r6, 0");
asm("    or      r0, r0, r0");
asm("    sbi     r3, r4, 0"); // ok

asm("    lbui    r3, r6, 0");
asm("    addi    r3, r3, 0");
asm("    sbi     r3, r4, 0"); // ok


This are the defines for write back
constant CFG_REG_FORCE_ZERO : boolean := true; 
constant CFG_REG_FWD_WRB    : boolean := true;
constant CFG_MEM_FWD_WRB    : boolean := true;

Many thanks for qualified help 
Edgar

Problem

I've tried to use the thesis instructions on how to synthesize an MB-lite design but they seem irrelevant. The instructions advised to include design files in mblite/design/core* directory, the design files are: (i) testbench.vhd which of course is not synthesizable and (ii) config_Pkg.vhd which is used as a configuration for the design. Improvising, I've included all the files in the hw directory. From then on, it is unclear to which file should be synthesize, possible candidates are core0 and core_wb (which should be an MB-lite core with a wishbone bus adapter). Also, some tutorial on software development would be helpful, I'm experimenting with ROM creation and possibly using the Xilinx SDK for Microblaze processor.

ISE synthesizing tutorial

Hi there!

How can I stall the processor properly while e.g. a time-consuming alu-operation is ongoing? I'm thinking about adding a FPU which will obviously not be able to operate in single clock cycles.

Thanks in advance

Stall within execute

Hi, I've spent a while getting MB-Lite to compile under the Xilinx tools.  I found that the trick of using 4 x 8 bit memories for dmem was necessary to prevent weird ISE synthesis crashes.  I discovered a bug in bin2vhd_4x8b.c while generating these memories: do0 - do3 are asynchronous in the generated VHDL, and should be moved inside the process(clk_i) section, as they are in bin2vhd_32b.c.  After I found this, simulation and synthesis were all correct.  Thanks for a useful project!

Register outputs in bin2vhd_4x8b.c

Hi!

We have encountered a problem with the branch-conditions. A BGT takes the branch even if the operand is zero. We looked into "execute.vhd" and hopefully fixed it:

Lines 205f should be altered to this:
WHEN BGT => v.branch := NOT dat_a(CFG_DMEM_WIDTH - 1) AND NOT zero;
WHEN BGE => v.branch := NOT dat_a(CFG_DMEM_WIDTH - 1);

Obviously you handled the ZERO in the BG*-branches like in the BL*-branches, which is lightly wrong ;)

Greetings

Wrong Branch-Conditions

Unless I am mistaken, there appears to be a bug in decode relating to the carry bit control.  It seems the default behavior should be assigned as KEEP instead of NOT_KEEP.

The default assignments in the comb and reg processes should be modified:
-        v.vctrl_ex.carry_keep := CARRY_NOT_KEEP;
+        v.ctrl_ex.carry_keep := CARRY_KEEP;

And the NOT_KEEP state should be added to the shift decode:
                 v.ctrl_ex.alu_op:= ALU_SHIFT;
+                v.ctrl_ex.carry_keep := CARRY_NOT_KEEP;
                 CASE instruction(6 DOWNTO 5) IS

I can provide an example that appears to trigger this if necessary.

decode: CARRY_NOT_KEEP

Looking at the mblite, it seems that there is no way to stall the processor to wait for data on the IMEM bus.  This would be advantageous since it allows a few additional options in interfacing with instruction memory: 

1) Allow use with slow memory or memories with different speeds
2) Allow use with bursty memories (like a cache)
3) Allow for the DATA and MEM to occupy the same memory and/or share a bus

While this doesn't help the performance at all, it certainly would seem to make the core more flexible, and allow mblite to more closely mirror the MicroBlaze architecture.

Has any thought gone into implementing something along these lines?

Modified Harvard Architecture

I tried to run the simulation in ghdl and got an error:

mblite/core_Pkg.vhd:402:33: object subtype is not locally static
mblite/core_Pkg.vhd:410:33: object subtype is not locally static
mblite/core_Pkg.vhd:422:33: object subtype is not locally static
mblite/core_Pkg.vhd:430:33: object subtype is not locally static

Patch the file and start to work normally

--- core_Pkg.vhd.orig	2009-11-17 08:52:40.000000000 +0300
+++ core_Pkg.vhd	2009-10-28 22:24:35.000000000 +0300
@@ -399,19 +399,25 @@
             -- Little endian decoding
             CASE size IS
                 WHEN byte => 
-                    CASE address(1 DOWNTO 0) IS
-                        WHEN "00"   => RETURN "000000000000000000000000" & data(CFG_DMEM_WIDTH/4 - 1 DOWNTO 0);
-                        WHEN "01"   => RETURN "000000000000000000000000" & data(CFG_DMEM_WIDTH/2 - 1 DOWNTO CFG_DMEM_WIDTH/4);
-                        WHEN "10"   => RETURN "000000000000000000000000" & data(3*CFG_DMEM_WIDTH/4 - 1 DOWNTO CFG_DMEM_WIDTH/2);
-                        WHEN "11"   => RETURN "000000000000000000000000" & data(CFG_DMEM_WIDTH - 1 DOWNTO 3*CFG_DMEM_WIDTH/4);
-                        WHEN OTHERS => RETURN "00000000000000000000000000000000";
-                    END CASE;
+                    if address(1 downto 0) = "00" then
+                        RETURN "000000000000000000000000" & data(CFG_DMEM_WIDTH/4 - 1 DOWNTO 0);
+                    elsif address(1 downto 0) = "01" then
+                        RETURN "000000000000000000000000" & data(CFG_DMEM_WIDTH/2 - 1 DOWNTO CFG_DMEM_WIDTH/4);
+                    elsif address(1 downto 0) = "10" then
+                        RETURN "000000000000000000000000" & data(3*CFG_DMEM_WIDTH/4 - 1 DOWNTO CFG_DMEM_WIDTH/2);
+                    elsif address(1 downto 0) = "11" then
+                        RETURN "000000000000000000000000" & data(CFG_DMEM_WIDTH - 1 DOWNTO 3*CFG_DMEM_WIDTH/4);
+                    else
+                        RETURN "00000000000000000000000000000000";
+                    end if;
                 WHEN halfword => 
-                    CASE address(1 DOWNTO 0) IS
-                        WHEN "00"   => RETURN "0000000000000000" & data(CFG_DMEM_WIDTH/2 - 1 DOWNTO 0);
-                        WHEN "10"   => RETURN "0000000000000000" & data(CFG_DMEM_WIDTH - 1 DOWNTO CFG_DMEM_WIDTH/2);
-                        WHEN OTHERS => RETURN "00000000000000000000000000000000";
-                    END CASE;
+                    if address(1 DOWNTO 0) = "00" then
+                        RETURN "0000000000000000" & data(CFG_DMEM_WIDTH/2 - 1 DOWNTO 0);
+                    elsif address(1 DOWNTO 0) = "10" then
+                        RETURN "0000000000000000" & data(CFG_DMEM_WIDTH - 1 DOWNTO CFG_DMEM_WIDTH/2);
+                    else
+                        RETURN "00000000000000000000000000000000";
+                    end if;
                 WHEN OTHERS =>
                     RETURN data;
             END CASE;
@@ -419,19 +425,25 @@
             -- Big endian decoding
             CASE size IS
                 WHEN byte => 
-                    CASE address(1 DOWNTO 0) IS
-                        WHEN "00"   => RETURN "000000000000000000000000" & data(CFG_DMEM_WIDTH - 1 DOWNTO 3*CFG_DMEM_WIDTH/4);
-                        WHEN "01"   => RETURN "000000000000000000000000" & data(3*CFG_DMEM_WIDTH/4 - 1 DOWNTO CFG_DMEM_WIDTH/2);
-                        WHEN "10"   => RETURN "000000000000000000000000" & data(CFG_DMEM_WIDTH/2 - 1 DOWNTO CFG_DMEM_WIDTH/4);
-                        WHEN "11"   => RETURN "000000000000000000000000" & data(CFG_DMEM_WIDTH/4 - 1 DOWNTO 0);
-                        WHEN OTHERS => RETURN "00000000000000000000000000000000";
-                    END CASE;
+                    if address(1 DOWNTO 0) = "00" then
+                        RETURN "000000000000000000000000" & data(CFG_DMEM_WIDTH - 1 DOWNTO 3*CFG_DMEM_WIDTH/4);
+                    elsif address(1 DOWNTO 0) = "01" then
+                        RETURN "000000000000000000000000" & data(3*CFG_DMEM_WIDTH/4 - 1 DOWNTO CFG_DMEM_WIDTH/2);
+                    elsif address(1 DOWNTO 0) = "10" then
+                        RETURN "000000000000000000000000" & data(CFG_DMEM_WIDTH/2 - 1 DOWNTO CFG_DMEM_WIDTH/4);
+                    elsif address(1 DOWNTO 0) = "11" then
+                        RETURN "000000000000000000000000" & data(CFG_DMEM_WIDTH/4 - 1 DOWNTO 0);
+                    else
+                        RETURN "00000000000000000000000000000000";
+                    end if;
                 WHEN halfword => 
-                    CASE address(1 DOWNTO 0) IS
-                        WHEN "00"   => RETURN "0000000000000000" & data(CFG_DMEM_WIDTH - 1 DOWNTO CFG_DMEM_WIDTH/2);
-                        WHEN "10"   => RETURN "0000000000000000" & data(CFG_DMEM_WIDTH/2 - 1 DOWNTO 0);
-                        WHEN OTHERS => RETURN "00000000000000000000000000000000";
-                    END CASE;
+                    if address(1 DOWNTO 0) = "00" then
+                        RETURN "0000000000000000" & data(CFG_DMEM_WIDTH - 1 DOWNTO CFG_DMEM_WIDTH/2);
+                    elsif address(1 DOWNTO 0) = "10" then
+                        RETURN "0000000000000000" & data(CFG_DMEM_WIDTH/2 - 1 DOWNTO 0);
+                    else
+                        RETURN "00000000000000000000000000000000";
+                    end if;
                 WHEN OTHERS =>
                     RETURN data;
             END CASE;

GHDL simulate

How you build for Xilinx? I get an error:

INTERNAL_ERROR:Xst:cmain.c:3446:1.47.6.1 -  To resolve this error, please consult the Answers Database and other online resources at http://support.xilinx.com 

You have an example project?

Build for Xilinx

a project should not be marked DONE
when no files are available for download or in SVN
hopefully the files will be available soon

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