Bergmann, Andreas

yuce, emrah

Krepa, Michal

Discrete Cosine Transform core

I am trying to run the testbench in this project using NVC (https://github.com/nickg/nvc).

I am using their recommended way to generate the simulation files using the command

`nvc -a MDCT_PKG.vhd MDCTTB_PKG.vhd ROMO.VHD ROME.VHD RAM.VHD CLKGEN.VHD DBUFCTL.VHD DCT1D.vhd DCT2D.VHD MDCT.VHD random1.vhd INPIMAGE.VHD MDCT_TB.VHD -e my_tb -r`

However, upon running this, I get an error which says
```** Error: expected type of range bound to be STD.STANDARD.REAL but is STD.STANDARD.INTEGER
	File MDCTTB_PKG.vhd, Line 47
              of REAL(ROMDATA_W-1 downto 0);```

Any help is greatly appreciated.

Unable to simulate testbench with NVC

The "mif" files pointed to in the rome_xil.vhd and romo_xil.vhd files are in this path: "c:/elektronika/dct/mdct/source/xilinx/....", I guess it should be a relative path ;)

By the way, in the Overview you mention this core has an 8 bit input and a 11 bit output, although, as far as I see, the output is 12 bits. Anyways, great job.

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Discrete Cosine Transform core