Name: minimips
Created: Jun 3, 2004
Updated: Dec 25, 2018
SVN Updated: Jun 18, 2009
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 1 reported / 0 solved
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Other project properties

Development status:Stable
Additional info:FPGA proven
WishBone compliant: No
WishBone version: n/a
License: LGPL

Main aspects

- The miniMIPS is a 32 bits core and has a Von Neumann architecture.

- The miniMIPS is 5-stage pipeline :
- Instruction extraction
- Instruction decoding
- Execution
- Memory access
- Update registers

- Only two instructions can access the memory. The others work on registers which are 32 bits large. The processor contains 32 registers.

- Data hazards are resolved thanks to a bypass unit.

- Branch hazards are resolved by predicting the address results.

- Interruptions and exceptions are taken in account thanks to a system coprocessor.


An assembly gasm is provided with the project to generate the binaries for the miniMIPS cores.
This program is developed by Samuel Hangouët and Louis-Marie Mouton.


The miniMIPS was integrated in an FPGA from Xilinx Xc2V1000-5fg456.

The processor speed is 50MHz. As at each cycle an instruction ends (except when there are stalls), that means 50 million instructions per second.

The processor is used as a free example in the XSmart-ICE product (a generic emulator for core) from the french society Raisonance based in Grenoble.


The project miniMIPS is a processor core based on the MIPS I architecture.

The project is born during a school project at the ENSERG (Ecole Nationale Supérieure d'Electronique et de Radioélectricité de Grenoble), France.

The main contributors are Samuel Hangouët, Sébastien Jan, Louis-Marie Mouton and Olivier Schneider.