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Name: minimips_superscalar
Created: Dec 21, 2018
Updated: Sep 15, 2019
SVN Updated: Mar 23, 2019
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 0 reported / 0 solved
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Other project properties

Development status:Alpha
Additional info:
WishBone compliant: No
WishBone version: n/a
License: LGPL


The miniMIPS Superscalar processor project started in March 2017 for a college project that explores levels of parallelism in various granularities and the author performed the work and presented it for the completion work of the Bachelor degree in Computer Engineering at UERGS
(State University of Rio Grande do Sul - Brazil) whose objective was to insert parallelism in the level of instructions.

The Superscalar miniMIPS processor is a 32-bit processor that has 2 pipelines. This processor was based on the "miniMIPS" processor that was created in 2004 and is hosted here at OPENCORES. The miniMIPS had its data path duplicated and can execute two instructions per clock cycle. The synthesized core requires a minimum clock period of 19.75 ns (50.6 MHz) according to the default static time analysis (you may set some false paths to achieve the frequency), so, its performance is equivalent to a pipeline synchronized by a clock of 100 MHz.

It is fully compatible with the miniMIPS ISA that implements the MIPS I microarchitecture. A new multiplication instruction has been created for operations with 16-bit operands and the result is saved directly to the general purpose register bank as the other logical and arithmetic instructions.

The GASM assembly that was created by the miniMIPS authors can be used to create programs. Was made available a modified version of GASM that assembles a multiplication instruction which operands are 16-bit wide.

* Let me know if any problem with my uploads or malfunction. *

miniMIPS with 2 pipelines

miniMIPS with 2 pipelines