Created: Dec 21, 2018
Updated: Jan 4, 2019
SVN Updated: Jan 4, 2019
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The miniMIPS Superscalar processor project started in March 2017 for a college project that explores levels of parallelism in various granularities and the author performed the work and presented it for the completion work of the Bachelor of Science degree in Computer Engineering at UERGS
(State University of Rio Grande do Sul - Brazil) whose objective was to insert parallelism in the level of instructions.
The Superscalar miniMIPS processor is a 32-bit processor that has 2 pipelines. This processor was based on the "miniMIPS" processor that was created in 2004 and is hosted here at OPENCORES. The miniMIPS has had its data path duplicated and can execute two instructions per clock cycle. It is fully compatible with the miniMIPS ISA that implements the MIPS I architecture. A new multiplication instruction has been created for operations with 16-bit operands and the result is saved directly to the general purpose register bank as the other logical and arithmetic instructions.
The GASM assembly that was created by the miniMIPS authors can be used to create programs. Was made available a modified version of GASM that assembles a multiplication instruction which operands are 16-bit wide.
The main maintainer is Miguel Cafruni.
miniMIPS with 2 pipelines
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