A hardware based system to decode JPEG baseline compressed image data. The different stages of the decoding process are implemented in a pipelined design described in VHDL. Running on a Virtex-II Pro FPGA at 100 MHz operation frequency. The pipelined structure allows for the processing of multiple image blocks simultanously. Thus, the decoder is prepared to decode MotionJPEG movies. Functionality of the system is demonstrated with a proof-of-concept hardware MotionJPEG video player application.
- jpeg baseline decoding
- display decoded data on a VGA monitor