OpenCores

MSP430 CPU core in VHDL

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Details

Name: msp430_vhdl
Created: Apr 24, 2014
Updated: Mar 7, 2019
SVN Updated: May 13, 2017
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 1 reported / 0 solved
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Other project properties

Category:Processor
Language:VHDL
Development status:Beta
Additional info:
WishBone compliant: No
WishBone version: n/a
License: LGPL

Description

This is an MSP430 CPU core in VHDL I created in 2010 as a feasibility project, based on the MSP430F1xx family.
The code is intended to be simple and efficient, the CPU itself is in a single file (cpu.vhd) including the state machine, memory interface with instruction decoder, register block, ALU and interrupt controller. The other files are for simulation and testing. Sys.vhd is an example main entity for synthesis in Altera Quartus II, tb.vhd is for simulation in Modelsim, VHDL Simili, etc.
"cpu instruction processing.xls" helps to understand the design.
Address space is 32k x 16bits, works with synchronous memory embedded in the FPGA.
Instruction cycle time compatibility with real MSP430 uC-s is not guaranteed.

Comprehensive verification was not done, only tested some of the instructions on a development board with Altera Cyclone II. The example code flashes the colors on a 800x600 VGA display.
Procedure to run software on the uC:
1. compile an assembly code with IAR Embedded Workbench for MSP430 (example in iar_test folder, asm.s43->test.a43).
2. convert the IAR output hex file to an Altera memory initialization file with hex2mif.bat (test.a43->ram_init.mif).
3. use ram_init.mif in the Quartus II project to initialize the RAM.