H.264/AVC Baseline Decoder

Overview

Nova is a low-power realtime H.264/AVC baseline decoder of QCIF resolution, targeting mobile applications. It is a dedicated, full hardwired and self-contained ASIC design without utilizing any GPP/DSP cores. It has been successfully verified on Xilinx Virtex-4 FPGA and 0.18um ASIC chip. The measured power consumption is 293uW@1V for 30fps QCIF decoding.

From April 30 2008, Ke Xu has the Copyright for nova. If you have interests of continuing to develop this core or implementing in commercial product, please drop me an email (eexuke@yahoo.com) for discussion.

Features

1.RTL coded in Verilog-HDL.
2.Support real-time H.264/AVC baseline decoding of QCIF resolution. Can be extended to higher resolutions via minor modifications.
3.Extensively pipelining & parallelism are utilized to improve the performance and reduce power.
4.Hybrid and self-adaptive pipeline architecture to avoid unnecessary stall cycles and to improve performance:
-Self-adaptive pipeline for both intra and inter prediction.
-4×4/16×16 hybrid pipeline.
-1×4 pixel column-level parallelism.
5.Low cost intra prediction unit:
-Self-adaptive pipeline.
-Hierarchical memory organization to reduce external memory access.
-“Seed” method for plane mode computation.
-Exploring data reuse between 1×4 columns.
-Multi-function Processing Elements for all intra prediction modes processing.
6.Optimized motion compensation (inter prediction) unit:
-Self-adaptive pipeline.
-Hierarchical memory organization to reduce external memory access.
-“Variable-block-shape” to reduce redundant memory access and improve throughput.
-On-chip reference pixel buffer to explore reference pixel reuse.
-Pipelined and parallelized luma interpolator, consisting of 9 horizontal 6-tap filters, 4 vertical 6-tap filters, and 4 bilinear filters.
-Innovative chroma interpolator utilizing smallest number of adders.
7.High performance deblocking filter:
-Innovative 5-stage pipeline architecture with data/structure hazards carefully managed.
-Single-port SRAM based, no dual/two-port SRAM required.
-204cycles/MB throughput with max. frequency of 200MHz (0.18µm process). Can deliver up to 980kMB/s throughput.
8.Manually inserted latch-based clock gating to reduce power.
9.Low-power, low-cost design:
-Requires only ~1.5MHz for QCIF 30fps real time decoding.
-Only 169k logic gates.
-Measured power consumption as low as 293µW@1V in 0.18um process.

Project News

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2009-08-11
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For better understanding of nova design, you can refer to the following documents:
1) Ke Xu, "Power-efficient Design Methodology for Video Decoding", PhD thesis, The Chinese University of Hong Kong, 2007.
2) Ke Xu, T. M. Liu, J. I. Guo, C. S. Choy, “Methods for Power/throughput/area Optimization of H.264/AVC Decoding”, Journal of Signal Processing Systems, 2009, DOI 10.1007/s11265-009-0408-6.
3) Ke Xu, C. S. Choy, “A 5-stage Pipeline, 204 Cycles/MB, Single-port SRAM Based Deblocking Filter for H.264/AVC”, IEEE Transactions on Circuits and Systems for Video Technology, vol. 18, issue 3, pp. 363 – 374, 2008.
4) Ke Xu, C. S. Choy, “A Power-efficient and Self-adaptive Prediction Engine for H.264/AVC Decoding”, IEEE Transactions on VLSI Systems, vol. 16, issue 3, pp. 302 - 313, 2008.
5) Ke Xu, C. S. Choy, C. F. Chan, K. P. Pun, “Power Efficient VLSI Realization of Complex FSM for H.264/AVC Bitstream Parsing”, IEEE Transactions on Circuits and Systems, Part II, vol. 54, issue 11, pp. 984 – 988, 2007.
6) Ke Xu, C. S. Choy, C. F. Chan, K. P. Pun, “Priority-based Heading One Detector in H.264/AVC Decoding”, EURASIP Journal on Embedded Systems, vol. 2007, Article ID 60834.
7) Ke Xu, C. S. Choy, “Low-power H.264/AVC Baseline Decoder for Portable Applications”, International Symposium on Low Power Electronics and Design, pp. 256 - 261, Sept. 2007, Oregon, USA.

You may send me an email to ask for my PhD thesis, while you can find other documents by Google or from IEEE website.

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2009-04-04
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The design of a multi-standard (MPEG-2/H.264/VC-1, may even include Chinese AVS) decoder which supports QCIF to HDTV 1080p resolution is launched. The decoder is based on original nova core and is scheduled to complete at the end of 2009 (or early 2010). Any interests of license this high-performance/low-cost/low-power IP, please contact me at eexuke@yahoo.com for more details.

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2008-05-02
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Specification, test files added.

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2008-04-30
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Verilog source code updated. Detailed specifications, documents, and test files to be updated soon.