pry, jon

mips compatible barrel processor

## Description

Octagon is a 32-bit mostly mips compatible 8-thread barrel processor. It is designed for LUT-6 architectures with LUT-ram and LUT-shift registers. It can reach speads in excess of 200mhz in Spartan-6.  
  
Some compiler settings are required to generate code compatible with Octagon. These are detailed in the example program. Mostly this results from lack of a branch delay slot. Supervisory instructions have different bits here and there and need to be watched out for when writing low-level codes.  
  
Current work is being done on adding MMU support so that the core will be able to run linux.  
  

## Getting the code

Code is available on GitHub at [https://github.com/jonpry](https://github.com/jonpry)octagon


<h2 id="description">Description</h2>
<p>Octagon is a 32-bit mostly mips compatible 8-thread barrel processor. It is designed for LUT-6 architectures with LUT-ram and LUT-shift registers. It can reach speads in excess of 200mhz in Spartan-6. <br />
<br />
Some compiler settings are required to generate code compatible with Octagon. These are detailed in the example program. Mostly this results from lack of a branch delay slot. Supervisory instructions have different bits here and there and need to be watched out for when writing low-level codes. <br />
<br />
Current work is being done on adding MMU support so that the core will be able to run linux. <br />
<br />
</p>
<h2 id="getting-the-code">Getting the code</h2>
<p>Code is available on GitHub at <a href="https://github.com/jonpry" target="_blank">https://github.com/jonpry</a>octagon</p>


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mips compatible barrel processor

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Getting the code