Koethe, Daniel

OPB PSRAM Controller

## Description

The OPB PSRAM-Controller connect a Pseudo-Staic-RAM, also named CellularRAM™ to the OPB-Bus.

## Features

Design  
\- max. 80 Mhz Memory Clock for a Spartan-3 1500 FPGA  
\- synchronous design, no DCM/DLL needed  
Performance with micron MT45W8MW16BGX-701  
\- 32-Bit Write: 3 Clock cycles  
\- 32-Bit Read: 8 Clock cycles  

## Status

\- Design Phase done  
\- Simulation Tests done  
\- Real-World Tests done


<h2 id="description">Description</h2>
<p>The OPB PSRAM-Controller connect a Pseudo-Staic-RAM, also named CellularRAM™ to the OPB-Bus. </p>
<h2 id="features">Features</h2>
<p>Design<br />
- max. 80 Mhz Memory Clock for a Spartan-3 1500 FPGA<br />
- synchronous design, no DCM/DLL needed<br />
Performance with micron MT45W8MW16BGX-701<br />
- 32-Bit Write: 3 Clock cycles<br />
- 32-Bit Read: 8 Clock cycles<br />
</p>
<h2 id="status">Status</h2>
<p>- Design Phase done<br />
- Simulation Tests done<br />
- Real-World Tests done<br />
</p>


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OPB PSRAM Controller

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