jshamlet

Hays, Kirk

Open8 uRISC

Desc: when an interrupt occurs, the control saves the return address onto the stack and jumps to the ISR. after executing the ISR, the RTI instruction is executed to return to normal mode of execution, where the stack is popped off to load the return address into the PC 

bug: the PC is not loaded with the return address but loaded with 0x0000 when RTI or RTS instructions are used. 

Solution: make the following changes into the code

when RTS_C1 =>
        CPU_Next_State       <= RTS_C2;
        AS_Ctrl.Src          <= ADDR_SP;
        SP_Ctrl.Oper         <= SP_POP;

    when RTS_C2 =>
        CPU_Next_State       <= RTS_C3;
        AS_Ctrl.Src          <= ADDR_SP;
        --Abishek start                                                                                                                                      
        Cache_Ctrl           <= CACHE_OPER1; --line added
        --Abishek end                                                                                                                                        
        -- if this is an RTI, then we need to POP the flags                                                                                                  
        if( SubOp = SOP_RTI )then
          SP_Ctrl.Oper       <= SP_POP;
        end if;
      when RTS_C3 =>
        CPU_Next_State       <= RTS_C4;
        --Abishek start                                                                                                                                      
        Cache_Ctrl           <= CACHE_OPER2;   --line added
        --Cache_Ctrl           <= CACHE_OPER1;  --original line                                                                                                             
        --Abishek end                                                                                                                                        
        -- It doesn't really matter what is on the address bus for RTS, while                                                                                
        --  it does for RTI, so we make this the default                                                                                                     
        AS_Ctrl.Src          <= ADDR_SP;
      when RTS_C4 =>
        CPU_Next_State       <= RTS_C5;
        --Abishek start                                                                                                                                      
        PC_Ctrl.Oper         <= PC_LOAD;   --these lines are added
        PC_Ctrl.Addr         <= Operand2 & Operand1;
        Cache_Ctrl           <= CACHE_OPER2;
        --Abishek end                                                                                                                                        
      when RTS_C5 =>
        CPU_Next_State       <= PIPE_FILL_0;
        --Abishek start                        
        --PC_Ctrl.Oper         <= PC_LOAD; --these lines are commented
        --PC_Ctrl.Addr         <= Operand2 & Operand1;                                                                                                       
        --Abishek end                                                                                                                                        
        if( SubOp = SOP_RTI )then
          CPU_Next_State     <= RTI_C6;
          Cache_Ctrl         <= CACHE_OPER1;
        end if;
      when RTI_C6 =>
        CPU_Next_State       <= PIPE_FILL_1;
        PC_Ctrl.Oper         <= PC_INCR;
        ALU_Ctrl.Oper        <= ALU_RFLG;
        ALU_Ctrl.Data        <= Operand1;
        PC_Ctrl.Oper         <= PC_INCR;
        Int_RTI_D            <= '1';

I have mailed you a detailed document reporting the bug and solution along with the waveforms for your convenience. Thanks
Abishek Ramdas

bug in the implementation of instructions RTI and RTS

The hexadecimal values in the comments at the ends of the following lines (lines 136 and 137 in the current Open8.vhd) do not reflect the declared binary values:

  constant ALU_UPP2          : OPCODE_TYPE := "10010"; -- x"11"
  constant ALU_RFLG          : OPCODE_TYPE := "10011"; -- x"12"

The lines should be:

  constant ALU_UPP2          : OPCODE_TYPE := "10010"; -- x"12"
  constant ALU_RFLG          : OPCODE_TYPE := "10011"; -- x"13"

This does not result in a bug, as the VHDL uses the binary values.

Comment mismatch in constant declarations

The comments on the ALU_MUL implementation in the VHDL indicate the N flag
is set by the operation, but the VHDL code does not do so.

ALU_MUL comments incorrect in VHDL

The BTT instruction on the open8 differs from that of the V8/ARClite.

The V8 version of the instruction uses the subop to
create a mask to test the desired bit of R0, and the 
inverse of the bit is set into the Z Flag:

BTT n
    Z = R0 & (1 << n) ? 0 : 1
    N = R0[7] & (1 << n)

On the Open8, the subop is used to address the register file, and the Z and N
flags are set according to the value of Rn:

BTT n
    Z = (Rn == 0)
    N = Rn[7]

The publicly available description of the BTT instruction for the V8 gives the operation as:

"if R0[#]=0, Set Z else clear Z"

Indicating the nth bit of R0, not the nth register in the register file, is the correct source to test.

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Open8 uRISC