Minimal PDP8/L implementation with 4K disk monitor system
Project maintainers
Details
Name: pdp8l
Created: May 27, 2013
Updated: May 28, 2013
SVN Updated: May 28, 2013
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 0 reported / 0 solved
Created: May 27, 2013
Updated: May 28, 2013
SVN Updated: May 28, 2013
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 0 reported / 0 solved
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Other project properties
Category:Processor
Language:VHDL
Development status:Beta
Additional info:FPGA proven
WishBone compliant: No
WishBone version: n/a
License: LGPL
Language:VHDL
Development status:Beta
Additional info:FPGA proven
WishBone compliant: No
WishBone version: n/a
License: LGPL
Description
This is an implementation of a Digital (DEC) PDP8/L processor with 4k memory, a single DF32 disk and serial interface. The project target is the ALTERA NEEK (Cyclone III EP3C25F324C6N). Run the 4K Disk Monitor System using only the FPGA chip. Download contains the complete Altera Quartus II (11.0) project directories with simulation files.
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