Plasma - most MIPS I(TM) opcodes

Hi, I tried to implement Plasma_Cpu on the Spartan-3A FPGA Starter Kit XC3S700A. I just change the spartan3e.ucf, but while the mapping, there is this error; MapLib:30 - LOC constraint N11 on SF_A<23> is invalid: No such site on the device. To bypass this error set the environment variable 'XIL_MAP_LOCWARN'.

I replaced the UCF constraints for the StrataFlash address pins, which correspond to the Intel StrataFlash Parallel NOR Flash (SF) Spartan 3E, with the UCF constraints for the Flash address pins Parallel NOR Flash PROM (NF)which correspond to the Spartan-3A FPGA Starter Kit XC3S700A.

Thank you drgbie

The message of the error is in fact the follow :

MapLib:30 - LOC constraint N11 on SF_A<23> is invalid: No such site on the device. To bypass this error set the environment variable 'XIL_MAP_LOCWARN'.

There was a discussion in the forum on using the Spartan-3A FPGA with the Plasma CPU:

http://opencores.org/forum,Cores,0,3413

The error was similar.

Does this help? Steve

Thank you this problem is solved. There is always the conflict between SF_A<0> and SF_D<15>. We read that NF_D<15> becomes NF_A<0> when NF_BYTE is asserted (for 8-bit mode) When I keep the both declarations, Pack:2811 - Directed packing was unable to obey the user design constraints (LOC=T17) which requires the combination of the symbols listed below to be packed into a single IOB component. The directed pack was not possible because: There is more than one pad symbol. The symbols involved are: BUF symbol "SF_D_15_IOBUF/IBUF" (Output Signal = N394) TBUF symbol "SF_D_15_IOBUF/OBUFT" (Control Signal = SPI_MISO_and0000_inv) PAD symbol "SF_D<15>" (Pad Signal = SF_D<15>) PAD symbol "SF_A<0>" (Pad Signal = SF_A<0>) If I put in comment one of the both : Place:866 - Not enough valid sites to place the following IOBs: IO Standard: Name = LVCMOS25, VREF = NR, VCCO = 2.50, TERM = NONE, DIR = BIDIR, DRIVE_STR = 12 SF_D<15> This may be due to either an insufficient number of sites available on the device, too many prohibited sites, or incompatible I/O Standards locked or range constrained to I/O Banks with valid sites. This situation could possibly be resolved by one (or all) of the following actions: a) Grouping IOBs of similar standards into a minimum amount of I/O Banks by using LOC or range constraints. b) Maximizing available I/O Banks resources for special IOBs by choosing lower capacity I/O Banks if possible. c) If applicable, decreasing the number of user prohibited sites or using a larger device.

How I can make ? Thank you