qrisc32 wishbone compatible risc core
Project maintainers
Details
Name: qrisc32
Created: Nov 16, 2010
Updated: Dec 5, 2011
SVN Updated: Dec 5, 2011
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 0 reported / 0 solved
Created: Nov 16, 2010
Updated: Dec 5, 2011
SVN Updated: Dec 5, 2011
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 0 reported / 0 solved
Star2you like it: star it!
Other project properties
Category:Processor
Language:Verilog
Development status:Alpha
Additional info:Specification done
WishBone compliant: No
WishBone version: n/a
License: LGPL
Language:Verilog
Development status:Alpha
Additional info:Specification done
WishBone compliant: No
WishBone version: n/a
License: LGPL
Description
Project Qrisc32 is academic research and implementation of 4 stages risc cpu. Testbench runs 3 different sorting algorithms on qrisc32 and shows cycles for each turn. For observing instruction set, please refer to "risc_report.pdf" file. For running simulation you can use Modelsim with run_sim.tcl file.
Qrisc32 is implemented by using SystemVerilog.
© copyright 1999-2018 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.