Generic AXI to APB bridge
Project maintainers
Details
Name: robust_axi2apb
Created: Mar 28, 2011
Updated: Apr 18, 2011
SVN Updated: Jul 3, 2011
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 0 reported / 0 solved
Created: Mar 28, 2011
Updated: Apr 18, 2011
SVN Updated: Jul 3, 2011
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 0 reported / 0 solved
Star9you like it: star it!
Other project properties
Category:System on Chip
Language:Verilog
Development status:Alpha
Additional info:
WishBone compliant: No
WishBone version: n/a
License: LGPL
Language:Verilog
Development status:Alpha
Additional info:
WishBone compliant: No
WishBone version: n/a
License: LGPL
Description
Generic AXI to APB bridge. Builds design according to required number of slaves, address decoding, AXI command depth, etc. Supports decode error, APB response delay and slave error. The source files are written in RobustVerilog, a free RobustVerilog parser can be downloaded from http://www.provartec.comedatools
© copyright 1999-2018 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.