It's a synthesizable parametric IP core of 32 bit RISC processor supporting full MIPS R2000 ISA, by using SystemC HDL. An optional CP0 coprocessor implementing full exception handling was also modelled. Also 64 bit pipeline multiplier supporting is optional, and pipeline depth is configurable.
Some bugs was fix.
-> correct bug when intterupt occur during MFLO and MFHI instruction.
Now I'm working on the CP0