Herveille, Richard

Simple General Purpose IO

## Description

Simple General Purpose IO port. It supports up to 8 GPIO pins. Each pin is individually programmable as either input or output. The core features an 8bit wishbone interface. Wider wishbone interfaces are easily supported by using multiple instances (e.g. 4 simple GPIO cores provide a 32bit wishbone interface).  
Very simple, very small.

## Features

\- Up to 8 GPIO pins per core  
\- Each GPIO pin individually programmable as either input or output  
\- Static synchronous design  
\- Fully synthesisable  
\- 11 LUTs in a Spartan-II, 43 LCELLs in an ACEX

## Status

Design is finished and available in Verilog from OpenCores CVS.


<h2 id="description">Description</h2>
<p>Simple General Purpose IO port. It supports up to 8 GPIO pins. Each pin is individually programmable as either input or output. The core features an 8bit wishbone interface. Wider wishbone interfaces are easily supported by using multiple instances (e.g. 4 simple GPIO cores provide a 32bit wishbone interface).<br />
Very simple, very small.</p>
<h2 id="features">Features</h2>
<p>- Up to 8 GPIO pins per core<br />
- Each GPIO pin individually programmable as either input or output<br />
- Static synchronous design<br />
- Fully synthesisable<br />
- 11 LUTs in a Spartan-II, 43 LCELLs in an ACEX</p>
<h2 id="status">Status</h2>
<p>Design is finished and available in Verilog from OpenCores CVS.</p>


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Simple General Purpose IO

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