Herveille, Richard

SPI core

I recently began experimenting with this SPI core.  In our application,
I felt that having a slave select generated by the state machine instead
of cpu controlled would help improve overall performance of the SPI interface.  I also added a register outside of the SPI core to be able to override the
state machine generated slave select.  That would provide the option of
holding slave select active between byte transfers.  I can make my
modification available in case you would be interested in adding it to
the design you have provided here.

Slave Select addition

Can someone explain how the numbers are related to the comments here:

        4'b0000: clkcnt <= #1 12'h0;   // 2   -- original M68HC11 coding
        4'b0001: clkcnt <= #1 12'h1;   // 4   -- original M68HC11 coding
        4'b0010: clkcnt <= #1 12'h3;   // 16  -- original M68HC11 coding
        4'b0011: clkcnt <= #1 12'hf;   // 32  -- original M68HC11 coding
        4'b0100: clkcnt <= #1 12'h1f;  // 8
        4'b0101: clkcnt <= #1 12'h7;   // 64
        4'b0110: clkcnt <= #1 12'h3f;  // 128
        4'b0111: clkcnt <= #1 12'h7f;  // 256
        4'b1000: clkcnt <= #1 12'hff;  // 512
        4'b1001: clkcnt <= #1 12'h1ff; // 1024
        4'b1010: clkcnt <= #1 12'h3ff; // 2048
        4'b1011: clkcnt <= #1 12'h7ff; // 4096

Baud rate

I download simple_spi_latest.tar.gz and extract it, but I cannot find spi_slave_model.v from bench directory. Can you provide it?

cannot find spi_slave_model.v from bench directory

In my simulations, it appears that in the case of running SCK at 1/2 the Wishbone clock rate causes problems.  All cases running at 1/4 the Wishbone clock appear to function properly.  Here is a summary of my simulation results with differenct SPCR control register combinations:

SPCR = 8'h50: extra SCK rising edge at end of byte
SPCR = 8'h51: correct functionality
SPCR = 8'h54: does not transmit first bit (only 7 SCK clocks)
SPCR = 8'h55: correct functionality
SPCR = 8'h58: extra SCK falling edge at end of byte
SPCR = 8'h59: correct functionality
SPCR = 8'h5C: does not transmit first bit (only 7 SCK clocks)
SPCR = 8'h5D: correct functionality

Please let me know if you can verify these results.

Thanks,
Nick

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SPI core