This package is a full-stack implementation of the AVR 2-stage pipeline, featuring synthesis for AVR2 (classic core), AVR2.5 (classic plus), AVR3 (with extended program memory), AVR4 (enhanced core) and AVR5 (enhanced core with extended program memory). Interrupts are supported with customized number of IRQ vector width.
The project comes with some example peripherals, such as UART, SPI, a basic timer, output port and SysTick timer.
FPGAs involved in the development and testing: This design has been synthetized and tested using various tools, including free & open source packages:
Software run by the core can seamlessly be built with the AVR-GCC toolchain. This bundle includes utilities aiding the conversion from ELF output to BRAM initializations (designed for iCE40 EBRs) or generic synchronous ROM interface to set up the initial program memory. A configurable startup code (crt0.s) is included in the package with options to be matched to the synthetized core architecture.
Flight heritage: This core, along with the peripherals included this package - and extended with custom ones - are in operation onboard the GRBAlpha nanosatellite since 2021-03-22. GRBAlpha is an 1U CubeSat technology demonstration mission where the goal is to validate the feasibility of detecting and characterizing gamma-ray bursts on such a small satellite.
This package is available from either OpenCores SVN or https://szofi.net/pub/verilog/softavrcore/. Select the softavrcore-latest.tar.gz file for the latest version. Comments are welcomed! Contact information: see ./core/avr_core.v.
On a Linux system, install the following toolchains and utilities:
make in the main directory. This will compile the example C code (found in ./build) and then run the synthesis and place-and-route targeted for the ICE40HX8K-B-EVN board. This step is automatically followed by the generation of the FPGA configuration bitstream for iCE40HX8K-CT256 (see the file top.bin).
On another operating systems and/or for non-Lattice FPGA targets:
By default, the example code (./build/main.c) sends the following series of messages via the built-in secondary UART interface of the ICE40HX8K-B-EVN board at 115200 baud:
[x] 0 => 0
[x] 1 => 1
[x] 2 => 4
[x] 3 => 9
[x] 4 => 16
[x] 5 => 25
[x] 6 => 36
Here the cadence is one message per second. The cores and the C code expect a 12MHz clock input for baud rate configuration and during the computation of the timer delay.
You may change the contents of the main() function to switch to another examples. Note also that the example is fitted for 1024 words of program code (i.e. 2048 bytes of program flash memory). Change top.v and ./build/Makefile accordingly for larger (or smaller) program memory configurations.