Koethe, Daniel

OPB SPI Slave 

## Description

The OPB SPI Core connects a FPGA to a DSP or Microprocessor as Slave-Device. This means all transfers are initiated by the Master an the FPGA-System only responds to read or write request.

## Features

\- OPB-Clock and SPI-Clock are complete independent  
\- SPI can run faster than OPB if guaranteed that no TX-FIFO Underrunn or RX- FIFO Overrunn occure.  
\- variable transfer length 2..32  
\- Automatic CRC-Generation for Transmit and Receive Data (only 8,32Bit Shift-Register Width)

## Status

\- simulation tests done  
\- Hardware tests on a Virtex-4 ML401 Board (LX25) done  
\- CRC-Code Real World Test in progress


<h2 id="description">Description </h2>
<p>The OPB SPI Core connects a FPGA to a DSP or Microprocessor as Slave-Device. This means all transfers are initiated by the Master an the FPGA-System only responds to read or write request.</p>
<h2 id="features">Features</h2>
<p>- OPB-Clock and SPI-Clock are complete independent<br />
- SPI can run faster than OPB if guaranteed that no TX-FIFO Underrunn or RX- FIFO Overrunn occure.<br />
- variable transfer length 2..32<br />
- Automatic CRC-Generation for Transmit and Receive Data (only 8,32Bit Shift-Register Width)</p>
<h2 id="status">Status</h2>
<p>- simulation tests done<br />
- Hardware tests on a Virtex-4 ML401 Board (LX25) done <br />
- CRC-Code Real World Test in progress<br />
</p>


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OPB SPI Slave

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