OpenCores

OPB SPI Slave :: Overview



Project maintainers

Details

Name: spi_slave
Created: Nov 19, 2007
Updated: May 15, 2008
SVN Updated: Mar 12, 2009
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 0 reported / 0 solved
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Other project properties

Category:Communication controller
Language:VHDL
Development status:Stable
Additional info:FPGA proven
WishBone compliant: No
WishBone version: n/a
License: LGPL

Description

The OPB SPI Core connects a FPGA to a DSP or Microprocessor as Slave-Device. This means all transfers are initiated by the Master an the FPGA-System only responds to read or write request.

Features

- OPB-Clock and SPI-Clock are complete independent
- SPI can run faster than OPB if guaranteed that no TX-FIFO Underrunn or RX- FIFO Overrunn occure.
- variable transfer length 2..32
- Automatic CRC-Generation for Transmit and Receive Data (only 8,32Bit Shift-Register Width)

Status

- simulation tests done
- Hardware tests on a Virtex-4 ML401 Board (LX25) done
- CRC-Code Real World Test in progress