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Taar Microprocessor :: Overview



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Name: taar
Created: Dec 16, 2017
Updated: Dec 12, 2018
SVN: No files checked in
Bugs: 0 reported / 0 solved
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Category:Processor
Language:Other
Development status:Planning
Additional info:
WishBone compliant: No
WishBone version: n/a
License: GPL

General processor overview

This project is still being designed ( on paper ) and I welcome anyone to contribute. This is an open source project.

The Taar processor is meant to be a clock-less, RISC-based, multi-core design. It is meant to be used mainly in desktop/mobile/embedded systems. The design is not related to any other processor.

To keep the architecture determinate ( real-time ) at hardware level, one of the simplifications is dividing the chip into three sections, each of which is similar but does different jobs but each section able to execute a maximum number of tasks ( processes ) to 100.

The first section runs general purpose programs, the second runs graphics rendering processes and the third runs network processes. The chip is fashioned as a System-on-Chip ( SoC ).

At the moment there are less than 20 instructions but with furthering of the design more instructions will of course be added.

The name Taar ( with a soft 'T' ) is derived from the Indian Hindi-language colloquialism for the old Telegram method of communication and relates to the Telegram's position as a real-time method relative to the other older methods of communication.


Register set for each ALU

The ALU ontains seven types of registers, as listed below along with their bit-length :

ALU busy status -------- 1 bit

Instruction ------------ 160 bits ( to contain the entire instruction )

R1 --------------------- 32 bits ( use explained later )

R2 --------------------- 32 bits ( use explained later )

R3 --------------------- 32 bits ( use explained later )

R4 --------------------- 32 bits ( use explained later )

Instruction pointer ---- 32 bits ( to hold the next instruction's address )

Only one of these seven registers is accessible to program code directly. Since the processor model uses “Instruction Interleaving” these registers are reloaded automatically for every task after each instruction is executed.


Instructions format

At present there are 17 instructions as given below as a single list :

loadreg-imm, loadreg-mem, storereg-byte, storereg-word, add, sub, and, or, xor, lsh, rsh, inv, jump, copyword, tas, callcxt, exitcxt


And then in further each instruction described in detail. Every Taar processor instruction is 160 bits long. The instructions are all of this fixed length and fixed format to allow the processor logic to read instructions at a determinate rate and keep things simple.

The instruction format is listed below in a vertical manner. The first line below is the first field of the instruction format from the right. The operands are being presented without names here because their usages are different for different Operation Code ( hereforth called opcode ). The numbers within the brackets are their bit-length :

Operation code -------- ( 32 bits )
Operand1 -------------- ( 32 bits )
Operand2 -------------- ( 32 bits )
Operand3 -------------- ( 32 bits )
Operand4 -------------- ( 32 bits )

The opcode field contains the precise instruction number that has to be executed by the execution core. Any user-mode program filling wrong operation code will be trapped at this point and terminated. A code section in the Main Control Program ( the kernel ) can possibly fill this field with wrong operation code. In that case, the processor entirely should halt and an appropriate external pin should become active or low. Actually only the first byte of the opcode contains the instruction number. The rest of this field should be filled with zeroes by software ( compiler ).


loadreg-imm and loadreg-mem instructions

Copy into register R1 the immediate value or the value from the memory address pointed to via Operand1.

loadreg-imm :

Usage ( lsb on top ) :
-------> opcode ( loadreg-imm )
-------> immediate value
-------> zero
-------> zero
-------> zero

Example :
---> loadreg-imm 0xfeedf00d 0, 0, 0


loadreg-mem :

Usage ( lsb on top ) :
-------> opcode ( loadreg-mem )
-------> the starting address
-------> the offset
-------> zero
-------> zero

Example :
---> loadreg-mem [0xf00df00d], 20, 0, 0


The loadreg instructions and their counterpart, the storereg instructions ( explained next ), exist because the mathematic and logic instructions do not access memory directly. Such partitioning allows allows keeping the ISA simple, small and clean. It also allows faster mathematic and logic instruction execution in one core versus relatively slower memory access in another core.


storereg-byte, storereg-word instructions

Copy a byte or a word into memory address the value from the register R1.

The mathematic and logic instructions don’t write back the result to memory after execution and therefore the code will have to use this instruction if a write-back is needed. Having a separate write-back will allow most instructions to access memory without too much queuing thus increasing hardware-level parallelism.

A second effect is that code that only compares and does not need the result value in memory, needn't take time for a write-back.

Usage ( lsb on top ) :
-------> opcode ( storereg-byte, storereg-word )
-------> the starting address
-------> the offset
-------> zero
-------> zero

Example :
---> storereg-byte [0xdead0000], 10, 0, 0


The eight mathematic and logic instructions : add, sub, and, or, xor, lsh, rsh, inv

The input for these instructions are taken from the registers R1 and R2. The result of operation is copied from R3 register to R1 register which allows the continuation of the mathematic or logic instructions in a branch out.


add == addition two numbers
sub == subtraction of two numbers
and == logical and'ing of two numbers
or == logical or'ing of two numbers
xor == logical exclusive or'ing of two numbers
lsh == left shifting of a number by so many places given in R2
rsh == right shifting a number by so many places given in R2
inv == invert a number


Usage ( lsb on top ) :
-------> opcode ( the mathematic or logic instruction )
-------> equal compare value
-------> less-than compare value
-------> jump on less-than
-------> jump on greater-than



After the operation, the instruction will act as below :


a. If the result contains the equal compare value, the automatically jumped-to address is of the instruction very next to the current instruction.

b. If the result is lesser than less-than compare value, the jump on less-than field is used to automatically jump to the relevant instruction's address.

c. Otherwise, the result is considered greater than the above values and the greater-than field is used to automatically jump to the relevant instruction's address.


This system is called “Conditional Jumps”. The automatically jumped-to addresses are absolute addresses.

jump instruction

Change the instruction pointer to the value in Operand1. Useful in creating loops.


Usage ( lsb on top ) :
-------> opcode ( jump )
-------> the 32-bit full address to jump to
-------> zero
-------> zero
-------> zero

Example :
---> jump [0xf00d0000], 0, 0, 0


copyword instruction

Copy a 32-bit word from one memory address to another address


[ Work In Progress ]


Usage ( lsb on top ) :
-------> opcode ( copyword )
-------> address of source pointer
-------> address of destination pointer
-------> zero
-------> zero


Copies a 32-bit word from source address to destination address, but both addresses use pointers to copy the data. This makes it easier to use consistent code. This instruction can be used in four ways :

(a). Doing a memory-to-memory copying, where both source address and destination address are incremented.


(b). Port-to-memory transfer, where the single port-read address ( source ) is held static but the destination address for i/o-read data-buffer is incremented.


(c). Memory-to-port transfer, where the i/o-write buffer address is incremented as source, but the destination i/o-write port-address is held static.


(d). Doing a processor-control-register-to-memory transfer, where both source address and destination address are incremented, but the destination address for i/o-read data-buffer is incremented.


(e). Other techniques.


Example :
---> copyword [0xabcddcba], [0xdcabbcda], 0, 0



tas instruction

Working with critical sections



[ Work In Progress ]



Usage ( lsb on top ) :
-------> opcode ( tas )
-------> address of tas word
-------> zero
-------> zero
-------> zero


The Taar implementation of atomic operations uses the tas instruction, which checks a given word for value equal to one. This ensures only one program has access to one “critical section port”. that critical section may contain important access to control program data structures which must be accessed serially.

[ To Be Done ]


callcxt and exitcxt instructions

The callcxt instruction initiates a special arrangement in the system, where this instruction when executed by user-level programs will lead the processor to change the instruction path to begin executing code from one of the “code contexts” available to the original program. The change of context is denoted by the context number. meaning that the specific function is identified by the function number in the first word after the callcxt. The exact number of bytes read after that ( the function arguments ) depend on the function number.

exitcxt gets the execution path to the original program.

These two calls exist because the Taar Main Control Program ( kernel ) is meant to be a microkernel and the two calls act as system calls into the service-providing user-level server tasks.


[ Work In Progress ]



Usage for callcxt ( lsb on top ) :
-------> opcode ( callcxt )
-------> context number
-------> call arguments data address
-------> zero
-------> zero


Usage for exitcxt ( lsb on top ) :
-------> opcode ( exitcxt )
-------> zero
-------> zero
-------> zero
-------> zero


Example :
---> callcxt 5, 0, 0, 0
---> exitcxt 0, 0, 0, 0


The contexts available to a user program are obtained by the program in its initial phase calling a service-name directory facility and getting attached with pointers relevant to needed services. The service-name directory is part of the kernel.

Hardware-assisted task scheduling

[ To be done ]

Memory Management

Taar uses a 32-bit address/data bus which means that it supports max 4 GB physical and virtual data.

[ To be done ]
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