Ternary (3-input) Adder :: Overview

Project maintainers


Name: ternary_adder
Created: Apr 3, 2013
Updated: Jan 14, 2015
SVN Updated: Apr 5, 2013
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 0 reported / 0 solved
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Other project properties

Category:Arithmetic core
Development status:Stable
Additional info:FPGA proven
WishBone compliant: No
WishBone version: n/a
License: Others


This IP core provides resource efficient ternary adders, i.e., adders with three inputs performing s = x + y + z, for the Altera and Xilinx platforms.
Resource efficient means that they need exactly the same resources on modern FPGAs as two-input adders, but are slightly slower.

A complete description can be found in the ternary adder documentation: http://opencores.orgusercontent,doc,1365162582

Note that the used method for the Xilinx ternary is patented (US patent no 7,274,211). Hence, only private, research or non-commercial use is allowed with this implementation!

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