Riedel, Ulrich

Tiny64

## Description Tiny64

A 64-Bit RISC CPU with minial resource usage. Every opcode is executed in 2 clock cycles.  
The word size is configurable via XLEN from 32 up to the FPGA limit. The assembler supports also  
differnet word sizes.  
Due simplicity TinyX supports no interrupts, cache, MMU, FPU.  
Interrupts may supported in the future.  
  
The assembler syntax is unusual. because jump instructions are coded  
as MOV to the R7 register.  
  
At March 2004 is was tested 32-Bit and 64-Bit in the Xilinx XC2S200 SpartanII.  

## Features Tiny64

2 clock cycles on all op-codes  
R7, the PC is equal handled like a normal register  

## Status Tiny64

March, 24th 2004 beta


<h2 id="description-tiny64">Description Tiny64</h2>
<p>A 64-Bit RISC CPU with minial resource usage. Every opcode is executed in 2 clock cycles.<br />
The word size is configurable via XLEN from 32 up to the FPGA limit. The assembler supports also<br />
differnet word sizes.<br />
Due simplicity TinyX supports no interrupts, cache, MMU, FPU.<br />
Interrupts may supported in the future.<br />
<br />
The assembler syntax is unusual. because jump instructions are coded<br />
as MOV to the R7 register.<br />
<br />
At March 2004 is was tested 32-Bit and 64-Bit in the Xilinx XC2S200 SpartanII.<br />
</p>
<h2 id="features-tiny64">Features Tiny64</h2>
<p>2 clock cycles on all op-codes<br />
R7, the PC is equal handled like a normal register<br />
</p>
<h2 id="status-tiny64">Status Tiny64</h2>
<p>March, 24th 2004 beta</p>


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Tiny64

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Description Tiny64

Features Tiny64

Status Tiny64