Tiny Instruction Set Computer

Project maintainers


Name: tisc
Created: Feb 24, 2009
Updated: Feb 27, 2009
SVN Updated: Mar 10, 2009
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 0 reported / 0 solved
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Other project properties

Development status:Beta
Additional info:
WishBone compliant: No
WishBone version: n/a


Simple minimal VHDL RISC processor.

Heavily inspired by Tim Böscke and his MCPU project (Avaiable here on opencores), the processor is an accumulator based machine with an index register.

The processor, like Tim's, was designed to fit in small FPGA or large CPLD.

License is free - do with it what you will. It would be nice if you credited me, however - we all have to work.

I have no idea if implementing this core will or will not violate patents, copyrights or cause any other type of lawsuits. I provide this core AS IS, without any warranties.


- Accumulator based machine
- 8 bit accumulator
- 8 bit index register

- Address modes
- immediate
- register
- indirect

- Harvard architecture
- 12 bit program word
- 10 bit Program counter
- 8 bit data memory
- 256 data memory addresses

- ALU with
- carry flag
- zero flag
- add, subtract, and nor

- 1 deep stack
- 7 states


- Fits into CPLD using an old version of Xilinx webpack
- As of 2001, never tested in hardware