totalcpu

TotalCPU

## Description

TotalCPU is RISC core with 12-bit instruction width and variable data width (from 12 to 64 bits). It is completely realized on Verilog-2001 and has two variants of implementation - with program counter placed in register block or defined as a standalone register. The first variant requires less hardware resources but it is almost 2 times slower then the second variant. It has its own instruction set that doesn’t depend upon data path width.  
  
the description and sources of TotalCPU are [http://www.opencores.org/cvsweb.shtml/totalcpu](http://www.opencores.org/cvsweb.shtml/totalcpu) (here)

## Status

\- Design done


<h2 id="description">Description</h2>
<p>TotalCPU is RISC core with 12-bit instruction width and variable data width (from 12 to 64 bits). It is completely realized on Verilog-2001 and has two variants of implementation - with program counter placed in register block or defined as a standalone register. The first variant requires less hardware resources but it is almost 2 times slower then the second variant. It has its own instruction set that doesn’t depend upon data path width.<br />
<br />
the description and sources of TotalCPU are <a href="http://www.opencores.org/cvsweb.shtml/totalcpu" target="_blank">http://www.opencores.org/cvsweb.shtml/totalcpu</a> (here)</p>
<h2 id="status">Status</h2>
<p>- Design done</p>


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TotalCPU

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