TTL Library
Project maintainers
Details
Name: ttl_library
Created: Apr 5, 2020
Updated: Apr 8, 2020
SVN Updated: Apr 6, 2020
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 0 reported / 0 solved
Created: Apr 5, 2020
Updated: Apr 8, 2020
SVN Updated: Apr 6, 2020
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 0 reported / 0 solved
Star3you like it: star it!
Other project properties
Category:Library
Language:VHDL
Development status:Beta
Additional info:
WishBone compliant: No
WishBone version: n/a
License: LGPL
Language:VHDL
Development status:Beta
Additional info:
WishBone compliant: No
WishBone version: n/a
License: LGPL
Description
Please write a description of the project here. It is used as a MetaTag (search engines looks at this).
A library of (many of) the standard TTL devices (7xxx series). A simple timing model is included. The aim is to support designs which will be implemented in the TTL discrete logic parts, so synthesis has not been a priority.
The url of the svn repository is: https://opencores.org/websvn/listing/ttl_library/ttl_library
© copyright 1999-2018 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.