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Details

Name: uart_block
Created: Apr 20, 2012
Updated: May 5, 2012
SVN Updated: May 12, 2012
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 0 reported / 0 solved
Star3you like it: star it!

Other project properties

Category:Communication controller
Language:VHDL
Development status:Mature
Additional info:FPGA proven, Specification done
WishBone compliant: Yes
WishBone version: n/a
License: LGPL

Description

Simple uart core with wishbone slave interface and programmable baud rate generator, based on clock speed and desired baud rate