Uart block
Project maintainers
Details
Name: uart_block
Created: Apr 20, 2012
Updated: May 5, 2012
SVN Updated: May 12, 2012
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 0 reported / 0 solved
Created: Apr 20, 2012
Updated: May 5, 2012
SVN Updated: May 12, 2012
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 0 reported / 0 solved
Star5you like it: star it!
Other project properties
Category:Communication controller
Language:VHDL
Development status:Mature
Additional info:FPGA proven, Specification done
WishBone compliant: Yes
WishBone version: n/a
License: LGPL
Language:VHDL
Development status:Mature
Additional info:FPGA proven, Specification done
WishBone compliant: Yes
WishBone version: n/a
License: LGPL
Description
Simple uart core with wishbone slave interface and programmable baud rate generator, based on clock speed and desired baud rate
© copyright 1999-2018 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.