Drange, Geir

Ultimate CRC

For the parallel implementation, Figure 2 timing diagram in the PDF file shows that loading data_i (n-bits wide) requires n clock cycles.  Shouldn't this be a single clock load of the n-bit data_i, and producing of parallel CRC in the next clock cycle?

Parallel data in requires N clocks?

hi,
I have to calculate crc32 of data length greater than 256 bytes and width may be up to 9000 bytes.how this code can be extended for require data width?

need of crc32 of  data width greater than 256 byes

I got some trouble with this core when I tried to simulate the parallel module with Modelsim 10.1. Almost all output signal were undefined. 
My solution:
Please add initial values to all signals and variables in the files ucrc_par.vhd and ucrc_ser.vhd. The end of the line can be 
:= (others => '0');
worked for me. Thanks.

Simulating with ModelSim

Hi,

I've included the crc module to my system. 
However when the module calculates the CRC, it releases me a 16 bit number instead of a 32 bit crc. 

One of the constraints of my proyect is that I have to calculate and add to the data sequence a 32 bit crc. Can I do this with this core?

I've a doubt

I have not been able to get 0's after clocking in data followed by the CRC value generated from the data.  Any idea why this is not happening?

Thanks!

Warren Chase

CRC checking

Initial values:
POLYNOMIAL = x"00018bb7"
INIT_VALUE = x”00000000”
DATA_WIDTH = 128
SYNC_RESET = 1
data_i = x”FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF”  (128 1’s)

The above would produce a 32-bit CRC output.

I am generating a good clock, reset, and clock enable.

The problem I am seeing is that the CRC never seems to converge using the above inputs. I never get a match_o signal high, and the crc_o is changing every clock cycle, never settling to a fixed value.

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Ultimate CRC